The present invention relates to the field of cell-based parallel processing systems. In particular, it relates to a parallel processing system composed of a regular collection of processing units whose behavior is controlled by software contained within each unit. More particularly, it relates to a processing system composed of processing units which operate in one of two modes, one mode being a data processing mode, and the other being a code processing mode.
Currently there are numerous varieties of programmable logic devices (PLDs) available, which contain fixed hardware but whose specific behavior can be controlled by loading some form of software into the device. Such devices include U.S. Pat. Nos. 5,550,782 and 4,034,356. These and other configurable devices combine the speed of custom hardware with the flexibility of software. As such they find application in rapid prototyping, field-upgradeable systems, and other applications potentially requiring changes to the hardware-level behavior of the system after it is manufactured. Traditionally, such changes are made while the system is disabled, and are generally performed by something (often a human) outside the system itself.
There has been much recent interest in self-reconfigurable systems, which undergo self modification while running. For example, a system composed of a PLD array might be initially configured to execute a certain algorithm, and another part of the system might monitor the performance of this algorithm. While the initial algorithm may be well suited for the initial class of input data, it may be that the nature of the input data changes over time, and eventually the algorithm becomes sub-optimal. The monitor could modify the algorithm accordingly, and then reconfigure the PLDs to execute the new algorithm. A typical application for such a system would be a deep-space satellite, which necessarily has a limited amount of hardware onboard (due to weight and space restrictions) and often encounters phenomenon not anticipated when the system was built.
There have been attempts to build such systems using current PLDs, especially Field Programmable Gate Arrays (FPGAs). Typically, these systems contain two main pieces: a PLD array (collection of interconnected PLDs) and a controller (which monitors the PLD array and modifies it as needed). While this works adequately for small, simple systems, there are some fundamental limitations to this approach, arising from the fact that the PLD array is not itself self-reconfigurable. Rather, it must be configured by some external controller. Generally this means that as the size of the PLD array grows, the external controller must also grow. Additionally, these PLDs are generally controlled through relatively narrow channels, creating bottlenecks when attempting simultaneous reconfiguration of multiple PLDs. Furthermore, since the controller is external to the PLD array, the individual PLDs need some form of addressibility, which makes scaling the array difficult. The system is also susceptible to critical failures, since the controller is the only piece of the system which can modify the PLDs (and hence represents a critical failure point). Finally, while the system can become quite sophisticated by virtue of the PLDs' programmability, the external controller remains fixed, and can not itself be enhanced via reprogramming of its hardware.
While there have been solutions to certain of these problems (eg. U.S. Pat. No. 4,845,633), such solutions don't address the fundamental limitation of current PLD designs. Namely, a PLD is configured by loading code into it, and that code affects how it processes data. However, the data and code are fundamentally separate entities. So, for example, one PLD can not read the code from another PLD, modify it, and write it into a third PLD. While enhancements can be made to allow specific actions such as this, current systems fail to achieve a fundamental duality between data processing and code processing.